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| DATA SHEET PD77110, 77111, 77112 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSORS MOS INTEGRATED CIRCUIT DESCRIPTION The PD77110, 77111, and 77112 are 16-bit fixed-point digital signal processors (DSPs). Compared with the PD77016 family, these DSPs have improved power consumption and are ideal for batterypowered mobile terminals such as PDAs and cellular phones. Both mask ROM and RAM models are available. For details of the functions of these DSPs, refer to the following User's Manuals: PD77111 Family User's Manual : To be available soon PD7701X Family User's Manual - Instructions: U13116E FEATURES z Instruction cycle (operating clock) PD77110 : 15.3 ns MIN (65 MHz MAX) 13.3 ns MIN (75 MHz MAX) (Operating voltage and ambient temperature are limited.) PD77111 : 13.3 ns MIN (75 MHz MAX) PD77112 : 13.3 ns MIN (75 MHz MAX) z Memory * Internal instruction memory PD77110 : RAM 35.5K words x 32 bits PD77111 : RAM 1K words x 32 bits Mask ROM 31.75K words x 32 bits PD77112 : RAM 1K words x 32 bits Mask ROM 31.75K words x 32 bits * Data memory PD77110 : RAM 24K words x 16 bits x 2 banks External memory space 32K words x 16 bits x 2 banks PD77111 : RAM 3K words x 16 bits x 2 banks Mask ROM 16K words x 16 bits x 2 banks PD77112 : RAM 3K words x 16 bits x 2 banks Mask ROM 16K words x 16 bits x 2 banks External memory space 16K words x 16 bits x 2 banks The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U12801EJ4V0DS00 (4th edition) Date Published November 1999 N CP(K) Printed in Japan The mark shows major revised points. (c) 1998, 1999 PD77110, 77111, 77112 ORDERING INFORMATION Part Number Package 100-pin plastic TQFP (fine pitch) (14 x 14 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm) 80-pin plastic fine-pitch BGA (9 x 9 mm) 100-pin plastic TQFP (fine pitch) (14 x 14 mm) PD77110GC-9EU PD77111GK-xxx-9EU PD77111F1-xxx-CN1 PD77112GC-xxx-9EU Remark xxx indicates ROM code suffix. 2 Data Sheet U12801EJ4V0DS00 BLOCK DIAGRAM X bus External memory Y bus Peripheral units Serial I/O #1 X memory data addressing unit Y memory data addressing unit R0 - R7 X memory Y memory Data memory unit Serial I/O #2 Main bus MPY 16 x 16 + 40 40 ALU (40) BSFT Data Sheet U12801EJ4V0DS00 Port Program control unit Host I/O Interrupt control Loop control stack PC stack Instruction memory Operation unit PD77110, 77111, 77112 CPU control PLL Wait controller INT1 - INT4Note 1 RESET WAKEUPNote 1 CLKOUT CLKIN PLL0 - PLL2Note 2 IE I/O Notes 1. The WAKEUP pin is multiplexed with the INT4 pin. With the PD77111 and 77112, the function of the WAKEUP pin can be activated or deactivated by mask option. With the PD77110, this function is always valid. 2. These pins are provided only on the PD77110. The PLL0 and PLL1 pins are multiplexed with the P2 and P3 pins. 3 PD77110, 77111, 77112 PIN CONFIGURATION +2.5 V +3 V Serial interface #1 SO1 SORQ1 SOEN1 SCK1 SI1 SIEN1 SIAK1 SO2 SOEN2 SCK2 SI2 SIEN2 (4) P0 - P3 IVDD EVDD RESET INT1 - INT4 CLKIN CLKOUT Reset, interrupt (4) Clock PLL0 - PLL2Note 1 WAKEUPNote 2 (3) System control Serial interface #2 Port (2) Host interface (8) For debugging (2) (4) HCS HA0, HA1 HRD HRE HWR HWE HD0 - HD7 DA0 - DA14Note 3 X/Y D0 - D15 MRD MWR HOLDRQ HOLDAK BSTB (15) External data (16) memory Note 4 Data bus control TDO, TICE TCK, TDI, TMS, TRST GND Notes 1. These pins are provided only on the PD77110. 2. With the PD77111 and 77112, the function of this pin can be activated or deactivated by mask option. With the PD77110, this function is always valid. 3. DA14 is not provided on the PD77112. 4. An external data memory interface is not provided on the PD77111. 4 Data Sheet U12801EJ4V0DS00 DSP FUNCTION LIST Item Memory space Internal instruction RAM (words x bits) Internal instruction ROM Data RAM (X/Y memory) Data ROM (X/Y memory) External instruction memory External data memory (X/Y memory) Instruction cycle (at maximum speed) Multiple 48K x 16 each 16K x 16 each 32K x 16 each None 16K x 16 each None 8K x 16 each 48K x 32 None PD77016 1.5K x 32 None 2K x 16 each PD77018A 256 x 32 PD77019 PD77019-013 PD77110 35.5K x 32 PD77111 PD77112 PD77113 PD77114 4K x 32 24K x 32 3K x 16 each None 1K x 32 31.75K x 32 3K x 16 each 3.5K x 32 48K x 32 16K x 16 each 24K x 16 each None 12K x 16 each None 16K x 16 each 32K x 16 each Data Sheet U12801EJ4V0DS00 30 ns (33 MHz) - 16.6 ns (60 MHz) x1, 2, 3, 4, 8 (mask option) Fixed to x4 15.3 ns (65 MHz) Integer of x1 to 8 (external pin) 13.3 ns (75 MHz) Integer of x1 to 16 (mask option) Serial interface (two channels) Channels 1 and 2 Channel 1 has same function as PD77016. Channel 2 does not have SORQ2 and SIAK2 pins (for connection of codec). have same function. 5V 3V DSP core: 2.5 V I/O pins : 3 V 80-pin TQFP 80-pin FBGA 100-pin TQFP 80-pin FBGA 100-pin TQFP Supply voltage PD77110, 77111, 77112 Package 160-pin QFP 100-pin TQFP 116-pin BGA 100-pin TQFP 5 PD77110, 77111, 77112 PIN CONFIGURATION 100-pin plastic TQFP (fine-pitch) (14 x 14 mm) (Top View) PD77110GC-9EU PD77112GC-xxx-9EU EVDD X/Y I.C. MRD MWR NU BSTB HOLDAK HOLDRQ INT1 INT2 INT3 INT4/WAKEUPNote 5 RESET GND IVDD TRST TMS TDI TCK TICE TDO GND IVDD GND 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 2 74 3 73 4 72 5 71 6 70 7 69 8 68 9 67 10 66 11 65 12 64 13 63 14 62 15 61 16 60 17 59 18 58 19 57 20 56 21 55 22 54 23 53 24 52 25 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 GND DA14/NCNote 1 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 D15 D14 D13 D12 D11 D10 D9 D8 EVDD EVDD CLKIN CLKOUT HA1 HA0 HWR HRD HCS HWE HRE GND EVDD HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 P0 P1 P2/PLL0Note 4 P3/PLL1Note 3 GND Notes 1. DA14 with PD77110, NC with PD77112 2. PLL2 with PD77110, NC with PD77112 3. P3 only for PD77112 4. P2 only for PD77112 5. With the PD77112, the function of the WAKEUP pin can be activated or deactivated by a mask option. 6 GND D7 D6 D5 D4 D3 D2 D1 D0 IVDD GND SI1 SIEN1 SCK1 SIAK1 SO1 SORQ1 SOEN1 SOEN2 SO2 SCK2 SIEN2 SI2 PLL2/NCNote 2 EVDD Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin Name GND DA14/NC DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 D15 D14 D13 D12 D11 D10 D9 D8 EVDD Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pin Name GND D7 D6 D5 D4 D3 D2 D1 D0 IVDD GND SI1 SIEN1 SCK1 SIAK1 SO1 SORQ1 SOEN1 SOEN2 SO2 SCK2 SIEN2 SI2 PLL2/NC EVDD Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Pin Name GND P3/PLL1 P2/PLL0 P1 P0 HD7 HD6 HD5 HD4 HD3 HD2 HD1 HD0 EVDD GND HRE HWE HCS HRD HWR HA0 HA1 CLKOUT CLKIN EVDD Pin No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin Name GND IVDD GND TDO TICE TCK TD1 TMS TRST IVDD GND RESET INT4/WAKEUP INT3 INT2 INT1 HOLDRQ HOLDAK BSTB NU MWR MRD I.C. X/Y EVDD Data Sheet U12801EJ4V0DS00 7 PD77110, 77111, 77112 80-pin plastic TQFP (fine-pitch) (12 x 12 mm) (Top view) PD77111GK-xxx-9EU EVDD NU NU INT1 INT2 INT3 INT4/WAKEUP RESET 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 GND NU NU NU NU NU NU NU NU EVDD GND NU NU NU NU NU NU NU NU EVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 65 64 63 62 61 TDO GND IVDD CLKIN GND GND IVDD TRST TMS TDI TCK TICE 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 40 EVDD CLKOUT HA1 HA0 HWR HRD HCS HWE HRE GND EVDD HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 GND 20 41 GND SI1 SIEN1 SCK1 SIAK1 SO1 SORQ1 SOEN1 SOEN2 SO2 IVDD GND SCK2 SIEN2 SI2 P3 8 Data Sheet U12801EJ4V0DS00 P2 P1 P0 EVDD PD77110, 77111, 77112 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name GND NU NU NU NU NU NU NU NU EVDD GND NU NU NU NU NU NU NU NU EVDD Pin No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Name GND SI1 SIEN1 SCK1 SIAK1 SO1 SORQ1 SOEN1 SOEN2 SO2 IVDD GND SCK2 SIEN2 SI2 P3 P2 P1 P0 EVDD Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Pin Name GND HD7 HD6 HD5 HD4 HD3 HD2 HD1 HD0 EVDD GND HRE HWE HCS HRD HWR HA0 HA1 CLKOUT EVDD Pin No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin Name GND CLKIN IVDD GND TDO TICE TCK TDI TMS TRST IVDD GND RESET INT4/WAKEUP INT3 INT2 INT1 NU NU EVDD Note Note The function of the WAKEUP pin can be activated or deactivated by a mask option. Data Sheet U12801EJ4V0DS00 9 PD77110, 77111, 77112 80-pin plastic fine-pitch BGA (9 x 9 mm) PD77111F1-xxx-CN1 (Bottom View) 9 8 7 6 5 4 3 2 1 J H G F E D C B A A B C D E F G H J (Top View) Index mark Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B8 B9 C1 C2 Pin Name EVDD NU INT2 INT4/WAKEUP IVDD TCK IVDD GND EVDD NU GND NU INT3 GND TDI GND CLKOUT HA1 NU NU Note Pin No. C3 C4 C5 C6 C7 C8 C9 D1 D2 D3 D4 D5 D6 D7 D8 D9 E1 E2 E3 E4 NU Pin Name Pin No. E6 E7 E8 E9 F1 F2 F3 F4 F5 F6 F7 F8 F9 G1 G2 G3 G4 G5 G6 G7 Pin Name HRE HD0 GND EVDD NU NU NU SIAK1 SOEN2 P2 HD1 HD3 HD2 NU NU SI1 SO1 SO2 SIEN2 HD6 Pin No. G8 G9 H1 H2 H3 H4 H5 H6 H7 H8 H9 J1 J2 J3 J4 J5 J6 J7 J8 J9 Pin Name HD4 HD5 NU NU SIEN1 SOEN1 GND SI2 P1 GND HD7 EVDD GND SCK1 SORQ1 IVDD SCK2 P3 P0 EVDD RESET TRST TICE CLKIN HA0 HWR NU NU NU INT1 TMS TDO HCS HRD HWE EVDD GND NU NU Note The function of the WAKEUP pin can be activated or deactivated by a mask option. 10 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 PIN NAME BSTB CLKIN CLKOUT D0 - D15 DA0 - DA14 EVDD GND HA0, HA1 HCS HD0 - HD7 HOLDAK HOLDRQ HRD HRE HWE HWR I.C. INT1 - INT4 IVDD MRD MWR NC NU P0 - P3 PLL0 - PLL2 RESET SCK1, SCK2 SI1, SI2 SIAK1 SIEN1, SIEN2 SO1, SO2 SORQ1 TCK TDI TDO TICE TMS TRST WAKEUP X/Y : Bus Strobe : Clock Input : Clock Output : 16-bit Data Bus : External Data Memory Address Bus : Power Supply for I/O Pins : Ground : Host Data Access : Host Chip Select : Host Data Bus : Hold Acknowledge : Hold Request : Host Read : Host Read Enable : Host Write Enable : Host Write : Internally Connected : Interrupt : Power Supply for DSP Core : Memory Read Output : Memory Write Output : Non-Connection : Not Used : Port : PLL Multiple Rate Set : Reset : Serial Clock Input : Serial Data Input : Serial Input Acknowledge : Serial Input Enable : Serial Data Output : Serial Output Request : Test Clock Input : Test Data Input : Test Data Output : Test In-Circuit Emulator : Test Mode Select : Test Reset : Wakeup from STOP Mode : X/Y Memory Select SOEN1, SOEN2 : Serial Output Enable Data Sheet U12801EJ4V0DS00 11 PD77110, 77111, 77112 CONTENTS 1. PIN FUNCTION ................................................................................................................................. 13 1.1 Pin Function Description .......................................................................................................... 13 1.2 Connection of Unused Pins...................................................................................................... 18 2. FUNCTION OUTLINE........................................................................................................................ 2.1 Program Control Unit ................................................................................................................ 2.2 Arithmetic Unit ........................................................................................................................... 2.3 Data Memory Unit ...................................................................................................................... 2.4 Peripheral Units ......................................................................................................................... 20 20 21 22 22 3. CLOCK GENERATOR ...................................................................................................................... 23 4. RESET FUNCTION ........................................................................................................................... 23 4.1 Hardware Reset.......................................................................................................................... 23 4.2 Initializing PLL ........................................................................................................................... 24 5. FUNCTIONS OF BOOT-UP ROM................................................................................................... 5.1 Boot at Reset.............................................................................................................................. 5.2 Reboot ........................................................................................................................................ 5.3 Signature Operation .................................................................................................................. 24 24 25 26 6. STANDBY MODES ........................................................................................................................... 26 6.1 HALT Mode................................................................................................................................. 26 6.2 STOP Mode................................................................................................................................. 27 7. MEMORY MAP .................................................................................................................................. 27 7.1 Instruction Memory ................................................................................................................... 27 7.2 Data Memory .............................................................................................................................. 29 8. MASK OPTION.................................................................................................................................. 8.1 Clock Control Options............................................................................................................... 8.2 WAKEUP Function..................................................................................................................... 8.3 Mask Option Equivalent Function of PD77110 ..................................................................... 30 30 31 31 9. INSTRUCTIONS ................................................................................................................................. 33 9.1 Outline of Instructions .............................................................................................................. 33 9.2 Instruction Set and Operation .................................................................................................. 34 10. ELECTRICAL SPECIFICATIONS ..................................................................................................... 40 11. PACKAGE .......................................................................................................................................... 72 12. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 75 12 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 1. PIN FUNCTION Because the pin numbers differ depending on the package, refer to the diagram of the package to be used. 1.1 Pin Function Description * Power supply Pin No. Pin Name 100-pin TQFP 35, 77, 85 25, 50, 64, 75, 100 1, 26, 36, 51, 65, 76, 78, 86 80-pin TQFP 31, 63, 71 10, 20, 40, 50, 60, 80 1, 11, 21, 32, 41, 51, 61, 64, 72 80-pin FBGA A5, A7, J5 A1, A9, E1, E9, J1, J9 A8, B2, B5, B7, E2, E8, H5, H8, J2 I/O Function Shared by: IVDD EVDD - - Power to DSP core (+2.5 V) Power to I/O pins (+3 V) - - GND - Ground - * System control Pin No. Pin Name 100-pin TQFP 74 73 87 53 52 49 80-pin TQFP 62 59 73 - - - 80-pin FBGA C7 B8 C4 - - - I/O Function Shared by: CLKIN CLKOUT RESET PLL0 PLL1 PLL2 Input Output Input Input Input Input System clock input Internal system clock output Internal system reset signal input PLL multiple setting input (PD77110 only) * Determines the PLL multiple at reset as followings: PLL2: PLL1: PLL0: 000 : Selects PLL multiple of x1. 001 : Selects PLL multiple of x2. 010 : Selects PLL multiple of x3. : 111 : Selects PLL multiple of x8. * These pins have no function on the PD77111 and 77112 . Stop mode release signal input. * When this pin is asserted active, the stop mode is released. The function of this pin can be activated or deactivated by a mask option. * This pin is always valid on the PD77110 . P2 P3 - - - WAKEUP 88 74 A4 Input INT4 Data Sheet U12801EJ4V0DS00 13 PD77110, 77111, 77112 * Interrupt Pin No. Pin Name 100-pin TQFP 91 - 89 80-pin TQFP 77 - 75 80-pin FBGA D4, A3, B4 A4 I/O Function Shared by: INT1 - INT3 Input External maskable interrupt input. * Detected at the falling edge. - INT4 88 74 Input WAKEUP * External data memory interface Pin No. Pin Name 100-pin TQFP 99 80-pin TQFP - 80-pin FBGA - I/O Function Shared by: X/Y Output (3S) Memory select signal output. 0: Uses X memory. 1: Uses Y memory. Address bus of external data memory. * Accesses the external memory. * Continuously outputs the external memory address accessed last when the external memory is not being accessed. Kept low (0x000) if the external memory is never accessed after reset. * DA14 is NC (no connection) and does not function on the PD77112. 16-bit data bus. * Accesses the external memory. Read output * External memory read Write output * External memory write Hold request signal * Input a low level to this pin when the external device uses the external data memory bus of the PD77110 and 77112. Bus strobe signal * This pin goes low when the PD77110 and 77112 use the external data memory bus. Hold acknowledge signal * This pin goes low when the external device is enabled to use the external data memory bus of the PD77110 and 77112. - DA0 - DA14 16 - 2 - - Output (3S) - D0 - D15 34 - 27, 24 - 17 97 - - - - - - - - I/O (3S) Output (3S) Output (3S) Input - - - - MRD MWR 96 HOLDRQ 92 BSTB 94 - - Output - HOLDAK 93 - - Output - Remark Pins marked "3S" under the heading "I/O" go into a high-impedance state in the following conditions: X/Y, DA0-DA14, MRD, MWR: When the bus is released (HOLDAK = low level) D0-D15: When the external data memory is not being accessed and when the bus is released (HOLDAK = low level) 14 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 * Serial interface Pin No. Pin Name 100-pin TQFP 39 42 43 41 80-pin TQFP 24 27 28 26 80-pin FBGA J3 J4 H4 G4 I/O Function Shared by: SCK1 SORQ1 SOEN1 SO1 Input Output Input Output (3S) Input Input Output Input Input Output (3S) Input Input Serial 1 clock input Serial output 1 request Serial output 1 enable Serial data output 1 - - - - - - - - - - - - SIEN1 SI1 SIAK1 SCK2 SOEN2 SO2 38 37 40 46 44 45 23 22 25 33 29 30 H3 G3 F4 J6 F5 G5 Serial input 1 enable Serial data input 1 Serial input 1 acknowledge Serial 2 clock input Serial output 2 enable Serial data output 2 SIEN2 SI2 47 48 34 35 G6 H6 Serial input 2 enable Serial data input 2 Remark The pins marked "3S" under the heading "I/O" go into a high-impedance state on completion of data transfer and input of the hardware reset (RESET) signal. Data Sheet U12801EJ4V0DS00 15 PD77110, 77111, 77112 * Host interface Pin No. Pin Name 100-pin TQFP 72 80-pin TQFP 58 80-pin FBGA B9 I/O Function Shared by: HA1 Input Specifies the register to be accessed by HD7 through HD0. * 1: Accesses the host interface status register (HST). * 0: Accesses the host transmit data register (HDT (out)) when read (HRD = 0), and host receive data register (HDT (in)) when written (HWR = 0). Specifies the register to be accessed by HD7 through HD0. * 1: Accesses bits 15 through 8 of HST, HDT (in), and HDT (out). * 0: Accesses bits 7 through 0 of HST, HDT (in), and HDT (out). Chip select input Host read input Host write input Host read enable output Host write enable output 8-bit host data bus - HA0 71 57 C8 Input - HCS HRD HWR HRE HWE HD0 - HD7 68 69 70 66 67 63 - 56 54 55 56 52 53 49 - 42 D7 D8 C9 E6 D9 E7, F7, F9, F8, G8, G9, G7, H9 Input Input Input Output Output I/O (3S) - - - - - - Remark The pins marked "3S" under the heading "I/O" go into a high-impedance state when the host interface is not being accessed. * I/O ports Pin No. Pin Name 100-pin TQFP 55 54 53 52 80-pin TQFP 39 38 37 36 80-pin FBGA J8 H7 F6 J7 I/O Function Shared by: P0 P1 P2 P3 I/O I/O I/O I/O General-purpose I/O port - - PLL0 PLL1 Note Note Note Only the PD77110. The PD77111 and 77112 have no multiplexed pins. 16 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 * Debugging interface Pin No. Pin Name 100-pin TQFP 79 80 81 82 83 84 80-pin TQFP 65 66 67 68 69 70 80-pin FBGA D6 C6 A6 B6 D5 C5 I/O Function Shared by: TDO TICE TCK TDI TMS TRST Output Output Input Input Input Input For debugging - - - - - - * Others Pin No. Pin Name 100-pin TQFP 98 80-pin TQFP - 80-pin FBGA - I/O Function Shared by: I.C. - - Internally connected. Leave this pin unconnected. No function pins. Connect these pins to EVDD. - - NU 95 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 14, 15, 16, 17, 18, 19, 78, 79 A2, B1, B3, C1, C2, C3, D1, D2, D3, E3, E4, F1, F2, F3, G1, G2, H1, H2 - NC 2, 49 - - No-connect pins (with PD77112). Leave these pins unconnected. - Caution If any signal is input to these pins or if an attempt is made to read these pins, the normal operation of the PD77110, 77111, and 77112 is not guaranteed. Data Sheet U12801EJ4V0DS00 17 PD77110, 77111, 77112 1.2 Connection of Unused Pins 1.2.1 Connection of Function Pins When mounting, connect unused pins as follows: Pin INT1 - INT4 X/Y DA0 - DA14 D0 - D15 Note 1 I/O Input Output Output I/O Output Input Output Input Input Input Input Output Output Output Input Input Output I/O I/O Input Output Input Input Output Connect to EVDD or GND. Connect to EVDD. Leave unconnected. Leave unconnected. Connect to GND. Connect to EVDD. Leave unconnected. Recommended Connection Connect to EVDD via pull-up resistor, or connect to GND via pull-down resistor. Leave unconnected. Connect to EVDD. Leave unconnected. Connect to EVDD or GND. MRD, MWR HOLDRQ BSTB, HOLDAK SCK1, SCK2 SI1, SI2 SIEN1, SIEN2 SOEN1, SOEN2 SORQ1 SO1, SO2 SIAK1 HA0, HA1 HCS, HRD, HWR HRE, HWE HD0 - HD7 P0 - P3 TCK TDO, TICE TMS, TDI TRST CLKOUT Note 2 Connect to EVDD via pull-up resistor, or connect to GND via pull-down resistor. Connect to GND via pull-down resistor. Leave unconnected. Leave unconnected. (internally pulled up). Leave unconnected. (internally pulled down). Leave unconnected. Notes 1. These pins may be left unconnected if the external data memory is not accessed in the program. However, connect these pins as recommended in the halt and stop modes when the power consumption must be lowered. 2. These pins may be left unconnected if HCS, HRD, and HWR are fixed to the high level. However, connect these pins as recommended in the halt and stop modes when the power consumption must be lowered. 18 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 1.2.2 Connection of no-function pins Pin I.C. NU NC I/O - - - Leave unconnected. Connect to EVDD. Leave unconnected. Recommended Connection Data Sheet U12801EJ4V0DS00 19 PD77110, 77111, 77112 2. FUNCTION OUTLINE 2.1 Program Control Unit This unit is used to execute instructions, and control branching, loops, interrupts, the clock, and the standby mode of the DSP. 2.1.1 CPU control A three-stage pipeline architecture is employed and almost all the instructions, except some instructions such as branch instructions, are executed in one system clock. 2.1.2 Interrupt control Interrupt requests input from external pins (INT1 through INT4) or generated by the internal peripherals (serial interface and host interface) are serviced. Multiple interrupts are also supported. 2.1.3 Loop control task A loop function without any hardware overhead is provided. A loop stack with four levels is provided to support multiple loops. 2.1.4 PC stack A 15-level PC stack that stores the program counter supports multiple interrupts and subroutine calls. 2.1.5 PLL A PLL is provided as a clock generator that can multiply or divide an external clock input to supply an operating clock to the DSP. The multiplication and division ratio are set as follows: * PD77110: A multiple of x1 to x8 is specified by an external pin (division ratio is fixed). * PD77111 and 77112: A multiple of x1 to x16 or a division ratio of 1/1 to 1/16 can be set by a mask option. Two standby modes are available for lowering the power consumption while the DSP is not in use. * HALT mode : Set by execution of the HALT instruction. The current consumption drops to several mA. The normal operation mode is recovered by an interrupt or hardware reset. * STOP mode: Set by execution of the STOP instruction. The current consumption drops to several 10 A. The normal operation mode is recovered by hardware reset or WAKEUP pin Note If the WAKEUP function is activated by mask option 2.1.6 Instruction memory The capacity and type of the memory differ depending on the model of the DSP. 64 words of the instruction RAM are allocated to interrupt vectors. A boot-up ROM that boots up the instruction RAM is provided, and the instruction RAM can be initialized or rewritten by self boot (boot from the internal data ROM or external data space) or host boot (boot via host interface). * PD77110: 35.5K-word RAM * PD77111, 77112: 1K-word RAM and 31.75K-word ROM Note The interrupt of each interrupt source can be enabled or disabled. . 20 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 2.2 Arithmetic Unit This unit performs multiplication, addition, logical operations, and shift, and consists of a 40-bit multiply accumulator, 40-bit data ALU, 40-bit barrel shifter, and eight 40-bit general-purpose registers. 2.2.1 General-purpose registers (R0 through R7) These eight 40-bit registers are used to input/output data for arithmetic operations, and load or store data from/to data memory. A general-purpose register (R0 to R7) is made up of three parts: R0L through R7L (bits 15 through 0), R0H through R7H (bits 31 through 16), and R0E through R7E (bits 39 through 32). Depending on the type of operation, RnL, RnH, and RnE are used as one register or in different combinations. 2.2.2 Multiply accumulator (MAC) The MAC multiplies two 16-bit values, and adds or subtracts the multiplication result from one 40-bit value, and outputs a 40-bit value. The MAC is provided with a shifter (MSFT: MAC ShiFTer) at the stage preceding the input stage. This shifter can arithmetically shift the 40-bit value to be added to or subtracted from the multiplication result 1 or 16 bits to the right . 2.2.3 Arithmetic logic unit (ALU) This unit inputs one or two 40-bit values, executes an arithmetic or logical operation, and outputs a 40-bit value. 2.2.4 Barrel shifter (BSFT: Barrel ShiFTer) The barrel shifter inputs a 40-bit value, shifts it to the left or right by any number of bits, and outputs a 40-bit value. The data may be arithmetically shifted to the right shifted to the right, in which case the data is sign-extended, or logically shifted to the right, in which case 0 is inserted from the MSB. Data Sheet U12801EJ4V0DS00 21 PD77110, 77111, 77112 2.3 Data Memory Unit The data memory unit consists of two banks of data memory and two data addressing units. 2.3.1 Data memory The capacity and type of the memory differ depending on the model of the DSP. All DSPs have two banks of data memory (X data memory and Y data memory). A 64-word peripheral area is assigned in the data memory space. * PD77110: RAM of 24K words x 2 banks * PD77111, 77112: RAM of 3K words x 2 banks and ROM of 16K words x 2 banks In addition, some models have an external data memory interface so that the external memory can be expanded. * PD77110: External data memory of 32K words x 2 banks * PD77112: External data memory of 16K words x 2 banks 2.3.2 Data addressing unit An independent data addressing unit is provided for each of the X data memory and Y data memory spaces. Each data addressing unit has four data pointers (DPn), four index registers (DNn), one modulo register (DMX or DMY), and an address ALU. 2.4 Peripheral Units A serial interface, host interface, general-purpose I/O port, and wait cycle register are provided. All these internal peripherals are mapped to the X data memory and Y data memory spaces, and are accessed from program as memory-mapped I/Os. 2.4.1 Serial interface (SIO) Two serial interfaces are provided. These serial interfaces have the following features: * Serial clock : Supplied from external source to each interface. The same clock is used for input and output on the interface. * Frame length: 8 or 16 bits, and MSB or LSB first selectable for each interface and input or output * Handshake : Handshaking with external devices is implemented with a dedicated status signal. With the internal units, polling, wait, or interrupt are used. 2.4.2 Host interface (HIO) This is an 8-bit parallel port that inputs data from or outputs data to an external host CPU or DMA controller. In the DSP, a 16-bit register is mapped to memory for input data, output data, and status. Handshaking with an external device is implemented by using a dedicated status signal. Handshaking with internal units is achieved by means of polling, wait, or interrupts. 2.4.3 General-purpose I/O port (PIO) This is a 4-bit I/O port that can be set in the input or output mode in 1-bit units. 22 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 2.4.4 Wait cycle register The number of wait cycles to be inserted when the external data memory area is accessed can be specified in advance by using a register (DWTR) Note . The number of wait cycles that can be set is 1, 3, or 7. Note This function is not available on the PD77111 because this DSP does not have an external data area. 3. CLOCK GENERATOR The clock generator generates an internal system clock based on the external clock input from the CLKIN pin and supplies the generated clock to the internal units of the DSP. For details of how to set the PLL multiple, refer to 4.2 Initializing PLL, 8.1 Clock Control Options, and 8.3.1 Settings related to clock control. Stop mode Halt mode CLKIN PLL control circuit xm Output divider /n Halt divider /l Internal system clock CLKOUT 4. RESET FUNCTION When a low level of a specified width is input to the RESET pin, the device is initialized. 4.1 Hardware Reset If the RESET pin is asserted active (low level) for a specified period, the internal circuitry of the DSP is initialized. If the RESET pin is then deasserted inactive (high level), boot processing of the instruction RAM is performed according to the status of the port pins (P0 and P1). After boot processing, processing is executed starting from the instruction at address 0x200 of instruction memory (reset entry). On power application, the RESET pin must be asserted active (low level) after 4 input clocks have been input with the RESET pin in the inactive status (high level), after the supply voltage has reached the level of the operating voltage. In other words, no power-ON reset function is available. On power application, the PLL must be initialized. Data Sheet U12801EJ4V0DS00 23 PD77110, 77111, 77112 4.2 Initializing PLL Initializing the PLL starts from the 1024th input clock after the RESET pin has been asserted active (low level). Initialization takes 1024 clocks and it takes the PLL 100 s to be locked. After that, the DSP operates with the set value of the PLL specified by a mask option (PD77111 or 77112) or an external pin (PD77110) when the RESET pin is deasserted inactive (high level). After initializing the PLL, be sure to execute boot-up processing to re-initialize the internal RAM. To initialize the PLL, the internal memory contents and register status of the DSP are not retained. If the RESET pin is deasserted inactive before the PLL initialization mode is set, the DSP is normally reset (the PLL is not initialized). CLKIN 1 RESET 1024 2048 Approx. 100 s PLL lock time PLL initialization (internal status) PLL initialization mode Caution Do not deassert the RESET signal inactive in the PLL initialization mode and during PLL lock period. 5. FUNCTIONS OF BOOT-UP ROM To rewrite the contents of the instruction memory on power application or from program, boot up the instruction RAM by using the internal boot-up ROM. The PD77110 has a function to verify the contents of the internal instruction RAM in the boot-up ROM. 5.1 Boot at Reset After hardware reset has been cleared, the boot program first reads the general-purpose I/O ports P0 and P1 and, depending on their bit pattern, determines the boot mode (self boot or host boot). After boot processing, processing is executed starting from the instruction at address 0x200 (reset entry) of the instruction memory. The pins (P0 and P1) that specify the boot mode must be kept stable for the duration of 3 clocks before and for the duration of 12 clocks after reset has been cleared (the clock is input from CLKIN). P1 0 0 1 1 P0 0 1 1 0 Boot Mode Does not execute boot but branches to address 0x200 Note . Executes host boot and then branches to address 0x200. Executes self boot and then branches to address 0x200. Setting prohibited Note This setting is used when the DSP must be reset to recover from the standby mode after reset boot has been executed once. 24 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 5.1.1 Self boot The boot-up ROM transfers the instruction code stored in the data memory space to the instruction RAM, based on the boot parameter written to address 0x4000 of the Y data memory. Generally, with a mask ROM model (PD77111 or 77112), this function is implemented by storing the instructions to be booted in the data ROM. In addition, the instructions to be booted can be also stored in an external data area in the form of flash ROM, and self boot can be executed from this external data area. With the PD77110, the value of address 0x4000 of the Y data memory is undefined on power application, because this address is in RAM. Therefore, with the PD77110, the self boot mode cannot be selected on power application, and host boot must be executed. This also applies when the PLL is initialized. By writing a boot parameter to address 0x4000 or those that follow of the Y data memory, self boot can be executed when the RESET signal is subsequently input (except the reset that initializes the PLL). In this case, however, the instructions to be booted are only those at address 0x0200 through 0x0FFF of the instruction RAM. 5.1.2 Host boot In this boot mode, a boot parameter and instruction code are obtained via the host interface, and transferred to the instruction RAM. With the PD77110, the host boot mode is used on power application. The boot instruction area is the instruction RAM from addresses 0x0200 through 0x0FFF. To boot up the instruction RAM from 0x4000 through 0xBFFF, host reboot is used. 5.2 Reboot By calling the next reboot entry from the program, the contents of the instruction RAM can be rewritten. In particular, the PD77110 has a reboot function that boots up the instruction RAM from 0x4000 through 0xBFFF. Reboot Mode Self boot X memory Word reboot Byte reboot Y memory Word reboot Byte reboot Host boot Host reboot Entry Address 0x2 0x4 0x1 0x3 0x6 (PD77110) 0x5 (PD77111, 77112) 5.2.1 Self reboot The instruction codes stored in the data memory are transferred to the instruction RAM. This boot mode cannot be used with the PD77110. Set the following parameters and call the entry address of the corresponding reboot mode to execute self reboot. * R7L : Number of instruction steps for rebooting * DP3: First address of X memory in which instruction codes are stored (in the case of reboot from X memory), or first address of the instruction memory to be loaded (in the case of reboot from Y memory) * DP7: First address of instruction memory to be loaded (in the case of reboot from X memory), or first address of X memory in which instruction codes are stored (in the case of reboot from Y memory) Data Sheet U12801EJ4V0DS00 25 PD77110, 77111, 77112 5.2.2 Host reboot An instruction code is obtained via the host interface and transferred to the instruction RAM. With the PD77110, the host reboot mode is used to boot up the instruction RAM from addresses 0x4000 through 0xBFFF. Areas 0x0200 through 0x0FFF and 0x4000 through 0xBFFF cannot be rebooted all at once. The entry address of the PD77110 is 0x6, and that of the PD77111 and 77112 is 0x5. Host reboot is executed by calling this address after setting the following parameter: * R7L : Number of instruction steps for rebooting * DP3: First address of instruction memory to be loaded 5.3 Signature Operation The PD77110 has a signature operation function so that the contents of the internal instruction RAM can be verified. The signature operation performs a specific arithmetic operation on the data in the instruction RAM booted up, and returns the result to a register. Perform the signature operation in advance on the device when it is operating normally, and repeat the signature operation later to check whether the data in RAM is correct by comparing the operation result with the previous result. If the results are identical, there is no problem. The entry address is 0x9. Execute the operation by calling this address after setting the following parameter. Note that the operation cannot be performed on the areas 0x0200 through 0x0FFF and 0x4000 through 0xBFFF at the same time. The operation result is stored in register R7. * R7L: Number of instruction steps for operation * DP3: First address of instruction memory for operation 6. STANDBY MODES Two standby modes are available. By executing the corresponding instruction, each mode is set and the power consumption can be reduced. 6.1 HALT Mode To set this mode, execute the HALT instruction. In this mode, functions other than clock circuit and PLL are stopped to reduce the current consumption. To release the HALT mode, use an interrupt or hardware reset. When releasing the HALT mode using an interrupt, the contents of the internal registers and memory are retained. It takes several 10 system clocks to release the HALT mode when the HALT mode is released using an interrupt. In the HALT Mode, the clock circuit of the PD77111 family supplies the following clock as the internal system clock. The clock output from the CLKOUT pin is as follows. The clock output from the CLKOUT pin, however, has a high-level width that is equivalent to 1 cycle of the normal operation (i.e., the duty factor is not 50%). * PD77110: 1/8 of internal system clock * PD77111, 77112: 1/l of internal system clock (l = integer from 1 to 16, specified by mask option) 26 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 6.2 STOP Mode To set this mode, execute the STOP instruction. In this mode, all the functions, including the clock circuit and PLL, are stopped and the power consumption is minimized with only leakage current flowing. To release the STOP mode, use hardware reset or WAKEUP pin. When releasing the STOP mode by using the WAKEUP pin, the contents of the internal registers and memory are retained, but it takes several 100 s to release the mode. The WAKEUP pin is multiplexed with the INT4 pin. Usually, this pin functions as an interrupt pin, but functions as the WAKEUP pin when it is asserted active in the STOP mode. Whether the WAKEUP pin is used to release the STOP mode is selected by mask option. For details, refer to 8.2 WAKEUP Function and 8.3.2 WAKEUP function. 7. MEMORY MAP A Harvard architecture, in which the instruction memory space and data memory space are separated is employed. 7.1 Instruction Memory 7.1.1 Instruction memory map The instruction memory space consists of 64K words x 32 bits, and the capacity and type of the memory differ depending on the product. PD77110 0xFFFF System 0xC000 0xBFFF System 0xBF00 0xBEFF PD77111, 77112 Internal instruction RAM (32K words) Internal instruction ROM (31.75K words) 0x4000 0x3FFF System 0x1000 0x0FFF Internal instruction RAM (3.5K words) 0x0240 0x023F Vector area (64 words) 0x0200 0x01FF System 0x0100 0x00FF Boot-up ROM (256 words) 0x0000 System 0x0600 0x05FF Internal instruction RAM (1K words) Vector area (64 words) System Boot-up ROM (256 words) Caution Programs and data cannot be placed at addresses reserved for the system, nor can these addresses be accessed. If these addresses are accessed, the normal operation of the device cannot be guaranteed. Data Sheet U12801EJ4V0DS00 27 PD77110, 77111, 77112 7.1.2 Interrupt vector table Addresses 0x200 through 0x23F of the instruction memory are entry points (vectors) of interrupts. instruction addresses are assigned to each interrupt source. Vector 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C INT1 INT2 INT3 INT4 SI1 input SO1 output SI2 input SO2 output HI input HO output Reserved Reset Reserved Interrupt Source Four Cautions 1. Although reset is not an interrupt, it is handled like an interrupt as an entry to a vector. 2. It is recommended that unused interrupt source vectors be used to branch an error processing routine. 3. Because a vector area also exists in the internal RAM area of the mask ROM model, this area must be booted up. not used. In addition, because the entry address after reset is 0x200, address 0x200 must be booted up even when the internal instruction RAM and interrupts are 28 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 7.2 Data Memory 7.2.1 Data memory map The data memory space consists of an X memory space and a Y memory space of 64K words x 16 bits each, and the memory capacity and memory type differ depending on the product. PD77110 0xFFFF PD77111 PD77112 External data memory (16K words) External data memory (32K words) 0x8000 0x7FFF System 0xC000 0xBFFF System Data RAM (16K words) 0x4000 0x3FFF 0x3840 0x383F 0x3800 0x37FF 0x3000 0x2FFF 0x2000 0x1FFF 0x1000 0x0FFF 0x0000 Data ROM (16K words) System Peripheral (64 words) Data ROM (16K words) System Peripheral (64 words) System Peripheral (64 words) System Data RAM (4K words) System Data RAM (4K words) 0x0C00 0x0BFF System System Data RAM (3K words) Data RAM (3K words) Caution Programs and data cannot be placed at addresses reserved for the system, nor can these addresses be accessed. If these addresses are accessed, the normal operation of the device cannot be guaranteed. Data Sheet U12801EJ4V0DS00 29 PD77110, 77111, 77112 7.2.2 Internal peripherals The internal peripherals are mapped to the internal data memory space. X/Y Memory Address 0x3800 0x3801 0x3802 0x3803 0x3804 0x3805 0x3806 0x3807 0x3808 0x3809 - 0x383F Register Name SDT1 SST1 SDT2 SST2 PDT PCD HDT HST DWTR Reserved area First serial data register First serial status register Second serial data register Second serial status register Port data register Port command register Host data register Host status register Data memory wait cycle register Caution Do not access this area. WTR - HIO IOP Function Peripheral Name SIO Cautions 1. The register names listed in this table are not reserved words of the assembler or the C language. Therefore, when using these names in assembler or C, the user must define them. 2. The same register is accessed, as long as the address is the same, regardless of whether the X memory space or Y memory space is accessed. 3. Even different registers cannot be accessed at the same time from both the X and Y memory spaces. 8. MASK OPTION The PD77111 and 77112 have mask options that must be specified when an order for a ROM is placed. This section explains these mask options. The mask options are specified in the Workbench (WB77016) development tool. To order a mask ROM, output a mask ROM ordering file format (.msk file) using WB77016. 8.1 Clock Control Options The following four clock related options must be specified. * PLL multiple * Output division ratio * HALT division ratio * Validity of CLKOUT pin 30 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 When the PLL multiple is m, output division ratio is n, and halt division ratio is l, the relationship between each operation mode and operating clock is as follows: Operation Mode Normal operation mode HALT mode STOP mode Clock Supplied Inside DSP m/n times external input clock m/n/l times external input clock Stopped The PLL control circuit multiplies the input clock by an integer from 1 to 16. Specify the mask option of the PLL multiple so that the multiplied frequency falls within the specified PLL lock frequency range. The output divider divides the clock multiplied by the PLL by an integer from 1 to 16. Specify the mask option of the output division ratio so that the frequency m/n times the external input clock supplied to the DSP falls within the specified operating frequency range of the DSP. The HALT divider functions only in the HALT mode. It divides the clock of the output divider by an integer from 1 to 16 and supplies the divided clock to the internal circuitry. Specify the mask option of the HALT division ratio so that necessary division can be performed. Whether the clock supplied to the internal circuitry of the DSP (internal system clock) is "output" or "not output" from the CLKOUT pin can be specified. Specify the mask option as necessary. If an odd value (other than 1) is specified as the output division ratio, the high-level width of the clock output from the CLKOUT pin is equal to one cycle during normal operation (i.e., the clock does not have a duty factor of 50%). 8.2 WAKEUP Function The WAKEUP pin can be used to release the STOP mode as well as a hardware reset. If the STOP mode is released by means of a hardware reset, the status before the STOP mode was set cannot be restored after the STOP mode has been released. If the WAKEUP pin is used, however, the status before the STOP mode is set can be retained and program execution can be resumed starting from the instruction after the STOP instruction. Whether the WAKEUP pin is used to release the STOP mode can be specified by a mask option. When the WAKEUP function is specified valid, the WAKEUP pin is multiplexed with the INT4 pin and it usually functions as an interrupt pin. The pin functions as the WAKEUP pin only in the STOP mode (if this pin is asserted active in the STOP mode, it is used only to release the STOP mode, and execution does not branch to an interrupt vector). 8.3 Mask Option Equivalent Function of PD77110 Because the PD77110 does not have mask options, the multiple of the PLL cannot be specified in the same manner as the PD77111 and 77112. However, an external pin on the PD77110 has a function equivalent to the mask option. Care must be exercised when using the PD77110, including when it is used to emulate the PD77111 and 77112. Data Sheet U12801EJ4V0DS00 31 PD77110, 77111, 77112 8.3.1 Settings related to clock control External pins PLL0 through PLL2 are used to set the multiple of the PLL. PLL0 and PLL1 are multiplexed with general-purpose I/O ports P2 and P3, and can be used as PLL setting pins only when it is so specified. The multiple must be an integer from 1 to 8. Operation Mode Normal operation mode HALT mode STOP mode Clock Supplied to DSP m times external input clock m/8 times external input clock Stopped For details on how to set the PLL multiple, refer to 4.2 Initializing PLL. Because the setting of PLL0 through PLL2 becomes valid in the PLL initialization mode, the value of PLL0 through PLL2 must be fixed before the PLL initialization mode is set. The option that makes CLKOUT pin output valid or invalid is fixed to "valid". 8.3.2 WAKEUP function The WAKEUP function of the PD77110 is fixed to "valid". 32 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 9. INSTRUCTIONS 9.1 Outline of Instructions An instruction consists of 32 bits. Almost all the instructions, except some such as branch instructions, are executed with one system clock. The maximum instruction cycle of the PD77110 is 15.3 ns. The maximum instruction cycle of the PD77111 and 77112 is 13.3 ns. The following nine types of instructions are available: (1) Trinomial operation instructions These instructions specify an operation by the MAC. As the operands, three general-purpose registers can be specified. (2) Binomial operation instructions These instructions specify an operation by the MAC, ALU, or BSFT. As the operands, two general-purpose registers can be specified. An immediate value can be specified for some of these instructions, instead of a general-purpose register, for one input. (3) Uninominal operation instructions These instructions specify an operation by the ALU. As the operands, one general-purpose register can be specified. (4) Load/store instructions These instructions transfer 16-bit values between memory and a general-purpose register. Any general-purpose register can be specified as the transfer source or destination. (5) Register-to-register transfer instructions These instructions transfer data from one general-purpose register to another. (6) Immediate value setting instructions These instructions write an immediate value to a general-purpose register and the registers of the address operation unit. (7) Branch instructions These instruction specify branching of program execution. (8) Hardware loop instructions These instruction specify repetitive execution of an instruction. (9) Control instructions These instructions are used to control the program. Data Sheet U12801EJ4V0DS00 33 PD77110, 77111, 77112 9.2 Instruction Set and Operation An operation is written in the operation field for each instruction in accordance with the operation representation format of that instruction. If two or more parameters can be written, select one of them. (a) Representation formats and selectable registers The following table shows the representation formats and selectable registers. Representation Format r0, r0, r0 rI, rI rh, rh re reh dp dn dm dpx dpy dpx_mod dpy_mod dp_imm *xxx R0 - R7 R0L - R7L R0H - R7H R0E - R7E R0EH - R7EH DP0 - DP7 DN0 - DN7 DMX, DMY DP0 - DP3 DP4 - DP7 DPn, DPn++, DPn--, DPn##, DPn%%, !DPn## (n = 0 - 3) DPn, DPn++, DPn--, DPn##, DPn%%, !DPn## (n = 4 - 7) DPn##imm (n = 0 - 7) Contents of memory with address xxx 34 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 (b) Modifying data pointer The data pointer is modified after the memory has been accessed. The result of modification becomes valid starting from the instruction that immediately follows. The data pointer cannot be modified. Example DPn DPn++ DPn-- DPn## Operation Nothing is done (value of DPn is not changed.) DPn DPn + 1 DPn DPn - 1 DPn DPn + DNn (Adds value of corresponding DN0 to DN7 to DP0 to DP7.) Example: DP0 DP0 + DN0 (n = 0 - 3) DPn = ((DPL + DNn) mod (DMX + 1)) + DPH (n = 4 - 7) DPn = ((DPL + DNn) mod (DMY + 1)) + DPH !DPn## Reverses bits of DPn and then accesses memory. After memory access, DPn DPn + DNn DPn DPn + imm DPn%% DPn##imm (c) Instructions that can be simultaneously written Instructions that can be simultaneously written are indicated by O. (d) Status of overflow flag (OV) The status of the overflow flag is indicated by the following symbol: z: Not affected : Set to 1 when overflow occurs Caution If an overflow does not occur as a result of an operation, the overflow flag is not reset but retains the status before the operation. Data Sheet U12801EJ4V0DS00 35 PD77110, 77111, 77112 Instruction Set Instructions Simultaneously Written Instruction Instruction Name Mnemonic Operation Trinomial Bino- Unino- Load/ Transmial minal store fer Immediatevalue Branch Control Flag Loop OV Trinomial operation Multiply add Multiply sub Sign unsign multiply add ro = ro + rh * rh ro = ro - rh * rh ro = ro + rh * rl (rl is in positive integer format.) ro ro + rh * rh ro ro - rh * rh ro ro + rh * rl { { { Unsign unsign multiply add 1-bit shift multiply add 16-bit shift multiply add Binomial operation Multiply Add Immediate add ro = ro + rl * rl ro ro + rl * rl (rl and rl' are in positive integer format.) ro ro 2 + rh * rh ro = (ro>>1) + rh * rh ro = (ro>>16) + rh * rh ro ro 216 + rh * rh { { { { { z z ro = rh * rh ro = ro + ro ro = ro + imm ro = ro - ro ro = ro - imm ro rh * rh ro ro + ro ro ro + imm (where imm 1) ro ro - ro ro ro - imm (where imm 1) ro ro >> rl ro ro >> imm Sub Immediate sub { Arithmetic right shift Immediate arithmetic right shift Logical right shift Immediate logical right shift ro = ro SRA rl { z z ro = ro SRA imm ro = ro SRL rl ro ro >> rl ro ro >> imm { z z ro = ro SRL imm Logical left shift ro = ro SLL rl Immediate logical left shift AND Immediate AND OR Immediate OR Exclusive OR Immediate exclusive OR ro = ro SLL imm ro ro << rl ro ro << imm ro ro & ro ro ro & imm ro ro ro ro ro imm ro ro ro ro ro imm { z z ro = ro & ro ro = ro & imm ro = ro ro ro = ro imm ro = ro ro ro = ro imm { z z { z z { z z 36 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 Instructions Simultaneously Written Instruction Instruction Name Mnemonic Operation Trinomial Bino- Unino- Load/ Transmial minal store fer Immediatevalue Branch Control Flag Loop OV Binomial operation Less than ro = LT (ro, ro) if (ro < ro) {ro 0x0000000001} else {ro 0x0000000000} ro 0x0000000000 ro ro + 1 ro ro - 1 if (ro < 0) {ro -ro} else {ro ro} ro ~ro ro -ro { z Uninominal operation Clear Increment Decrement Absolute value CLR (ro) ro = ro + 1 ro = ro - 1 ro = ABS (ro) { { { { { { { { z 1's complement 2's complement Clip ro = ~ro ro = -ro { { { { { { z ro = CLIP (ro) if ( ro > 0x007FFFFFFF) {ro 0x007FFFFFFF} elseif {ro < 0xFF80000000} {ro 0xFF80000000} else {ro ro} z Round ro = ROUND (ro) if (ro > 0x007FFF0000) {ro 0x007FFF0000} elseif {ro < 0xFF80000000} {ro 0xFF80000000} else {ro (ro + 0x8000) & 0xFFFFFF0000} 1 ro log2 ( ro) ro ro ro ro + ro ro ro - ro if (sign (ro) == sign (ro)) {ro (ro - ro) << 1} else {ro (ro + ro)<<1} if (sign (ro)==0) {ro ro + 1} { { z Exponent Substitution Accumulated addition Accumulated subtraction Division ro = EXP (ro) ro = ro ro + = ro ro - = ro { { { { { { { { { { z z ro / = ro Data Sheet U12801EJ4V0DS00 37 PD77110, 77111, 77112 Instructions Simultaneously Written Instruction Instruction Name Mnemonic Operation Trinomial Bino- Unino- Load/ Transmial minal store fer Immediatevalue Branch Control Flag Loop OV Load/ store Parallel Notes 1, 2 load/store ro = *dpx_mod ro = *dpy_mod ro = *dpx_mod *dpy_mod = rh *dpx_mod = rh ro = *dpy_mod *dpx_mod = rh *dpy_mod = rh ro *dpx, ro *dpy ro *dpx, *dpy rh *dpx rh, ro *dpy *dpx rh, *dpy rh dest *dpx, dest *dpy dest *dpx, *dpy source *dpx source, dest *dpy *dpx source, *dpy source dest *addr *addr source dest *dp *dp source dest rl rl source rl imm dp imm dn imm dm imm { { { z Partial load/ Notes 1, 2, 3 store dest = *dpx_mod dest = *dpy_mod dest = *dpx_mod *dpy_mod = source *dpx_mod = source dest = *dpy_mod *dpx_mod = source *dpy_mod = source z Direct addressing Note 4 load/store Immediate value index Note 5 load/store Register- Register-toto-register register Note 6 transfer transfer Immediate value setting Immediate value setting dest = *addr *addr = source dest = *dp_imm *dp_imm = source dest = rl rl = source rl = imm (where imm = 0 to 0xFFFF) dp = imm (where imm = 0 to 0xFFFF) dn = imm (where imm = 0 to 0xFFFF) dm = imm (where imm = 1 to 0xFFFF) z z { z z Notes 1. Of the two mnemonics, either one of them or both can be written. 2. After transfer, modification specified by mod is performed. 3. Select any of dest, dest' = {ro, reh, re, rh, rl}, source, source' = {re, rh, rl}. 0: X-0xFFF : X (X memory) . 4. Select any of dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}, addr = 0: Y-0xFFFF : Y (Y memory) 5. Select any of dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}. 6. Select any register other than general-purpose registers as dest and source. 38 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 Instructions Simultaneously Written Instruction Instruction Name Mnemonic Operation Trinomial Bino- Unino- Load/ Transmial minal store fer Immediatevalue Branch Control Flag Loop OV Branch Jump Register indirect jump Subroutine call JMP imm JMP dp PC imm PC dp SP SP + 1 STK PC + 1 PC imm SP SP + 1 STK PC + 1 PC dp PC STK SP SP - 1 PC STK STK SP - 1 Recovery of interrupt enable flag Start During repeat End RC count RF 0 PC PC RC RC - 1 PC PC + 1 RF 1 RC count RF 0 PC PC RC RC - 1 PC PC + 1 RF 1 { { { z z z CALL imm Register indirect subroutine call Return CALL dp { z RET { { z z Interrupt return RETI Hardware loop Repeat REP count z Loop LOOP count (instruction of two or more lines) Start During repeat End z Loop hop LPOP LC LSR3 LE LSR2 LS LSR1 LSP LSP - 1 PC PC + 1 CPU stops. CPU, PLL, and OSC stop. Condition test Discard interrupt request { { { z Control No operation Halt Stop NOP HALT STOP z z z z z Condition IF (ro cond) Forget interrupt FINT Data Sheet U12801EJ4V0DS00 39 PD77110, 77111, 77112 10. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = +25C) Parameter Supply voltage Symbol IVDD EVDD Input voltage Output voltage Storage temperature Operating temperature VI VO Tstg TA Condition For DSP core For I/O pins VI < EVDD + 0.5 V Rating - 0.5 to +3.6 -0.5 to +4.6 -0.5 to +4.1 -0.5 to +4.1 -65 to +150 -40 to +85 Unit V V V V C C Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. The absolute maximum ratings are values that may physically damage the product(s). Be sure to use the product(s) within the ratings. Recommended Operating Conditions PD77110 Parameter Operating voltage Symbol IVDD EVDD Input voltage VI Condition For DSP core For I/O pins MIN. 2.3 2.7 0 TYP. MAX. 2.7 3.6 EVDD Unit V V V PD77111, 77112 Parameter Operating voltage Symbol IVDD EVDD Condition For DSP core For I/O pins IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V 0 MIN. 1.8 2.7 TYP. MAX. 2.7 3.3 3.6 EVDD V Unit V V Input voltage VI Capacitance (TA = +25C, IVDD = 0 V, EVDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CI CO CIO Condition f = 1 MHz, Pins other than those tested: 0 V MIN. TYP. 10 10 10 MAX. Unit pF pF pF 40 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 DC Characteristics (TA = -40 to +85C, with IVDD and EVDD within recommended operating condition range) Parameter High-level input voltage Symbol VIHN VIHS Condition Pins other than below CLKIN, RESET, INT1 - INT4, SCK1, SIEN1, SOEN1, SCK2, SIEN2, SOEN2 MIN. 0.7 EVDD 0.8 EVDD TYP. MAX. EVDD EVDD Unit V V Low-level input voltage High-level output voltage VIL VOH LOH = -2.0 mA IOH = -100 A 0 0.7 EVDD 0.8 EVDD 0.2 EVDD V V V Low-level output voltage High-level input leakage current Low-level input leakage current Pull-up pin current Pull-down pin current Internal supply current [VIHN = VIHS = EVDD, VIL = 0 V, no load] VOL ILH IOL = 2.0 mA Other than TDI, TMS, and TRST VI = EVDD Other than TDI, TMS, and TRST VI = 0 V TDI, TMS, 0 V VI EVDD TRST, 0 V VI EVDD During operating, 30 ns, IVDD = 2.7 V In halt mode, tcC = 30 ns, divided by eight, IVDD = 2.7 V In stop mode, 0C < TA < 60C 0 -10 -250 0 TBD 0.2 EVDD 10 V A A A A mA ILL 0 IPUI IPDI IDD Note 1 0 250 75 IDDH TBD 10 Note 2 mA IDDS 100 A Notes 1. The TYP. values are when an ordinary program is executed. The MAX. values are when a special program that brings about frequent switching inside the device is executed. 2. Values of PD77111 and 77112. The parameters of the PD77110 are still under evaluation. Common Test Criteria of Switching Characteristics CLKIN, RESET, INT1 - INT4, SCK1, SIEN1, SOEN1, SCK2, SIEN2, SOEN2 0.8 EVDD 0.5 EVDD 0.2 EVDD 0.8 EVDD 0.5 EVDD 0.2 EVDD Test points Input (other than above) 0.7 EVDD 0.5 EVDD 0.2 EVDD Test points 0.7 EVDD 0.5 EVDD 0.2 EVDD Output 0.5 EVDD Test points 0.5 EVDD Data Sheet U12801EJ4V0DS00 41 PD77110, 77111, 77112 PD77110 (1) PD77110 AC Characteristics (Unless otherwise specified, TA = -40 to +85C, with IVDD and EVDD within recommended operating condition range) Clock Timing requirements Parameter CLKIN cycle time Note 1 Symbol tcCX Condition MIN. 25 TYP. MAX. Unit ns PLL lock range CLKIN high-level width CLKIN low-level width CLKIN rise/fall time Internal clock cycle time Note 3 requirements twCXH twCXL trfCX tcC (R) Note 2 10 x m 12.5 12.5 50 x m ns ns ns 5 15.3 ns ns Notes 1. m: Multiple 2. This is the range in which the PLL is locked (stably oscillates). Input tcCX within this range. 3. Input tcCX so that the value of (tcCX / m) satisfies this condition. Timing requirements (TA = -40 to +60C, IVDD = 2.5 to 2.7 V, EVDD = 2.7 to 3.6 V) Parameter CLKIN cycle time Note 1 Symbol tcCX Condition MIN. 25 TYP. MAX. Unit ns PLL lock range CLKIN high-level width CLKIN low-level width CLKIN rise/fall time Internal clock cycle time Note 2 requirements twCXH twCXL trfCX tcC (R) Note 2 10 x m 12.5 12.5 50 x m ns ns ns 5 13.3 ns ns Notes 1. m: Multiple 2. This is the range in which the PLL is locked (stably oscillates). Input tcCX within this range. 3. Input tcCX so that the value of (tcCX / m) satisfies this condition. 42 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 PD77110 Switching characteristics Parameter Internal clock cycle Note Symbol tcC Condition During normal operation In HALT mode MIN. TYP. tcCX / m tcCX / m x l tcC MAX. Unit ns ns ns ns ns CLKOUT cycle time CLKOUT width tcCO twCO During normal operation In HALT mode tcCX / 2 - 3 tcCX / m - 3 CLKOUT rise/fall time CLKOUT delay time trfCO tdCO 5 15 ns ns Note m: Multiple, l: HALT division ratio Clock I/O timing tcCX twCXH twCXL trfCX trfCX CLKIN tcC, tcC (R) Internal clock tcCO tdCO twCO twCO trfCO trfCO CLKOUT Data Sheet U12801EJ4V0DS00 43 PD77110, 77111, 77112 PD77110 Reset, Interrupt Timing requirements Parameter RESET low-level width Symbol tw (RL) Condition On power application in STOP mode During normal operation, in HALT mode RESET recovery time trec (R) On power application Note 4 Note 1 MIN. , 100 + 2048tcCX 4tcC Note 2 TYP. MAX. Unit s Note 3 ns 4tcCX 4tcC Note 2 ns ns WAKEUP low-level width INT1 - INT4 low-level width INT1 - INT4 recovery time tw (WAKEUPL) tw (INTL) trec (INT) 100 3tcC Note 2 s ns ns 3tcC Notes 1. The value on power application is the time from when the supply voltages have reached IVDD = 1.8 V and EVDD = 2.7 V. A stable clock input is also required. 2. Note that tcC is eight times this value during normal operation in the HALT mode. 3. If the low-level width of RESET is greater than 1024tcC, the PLL initialization mode is triggered. If there is no need to use the PLL initialization mode, set the width to less than 1024tcC. 4. When the power is turned on, a recovery period of 4tcCX is necessary before inputting RESET. Reset timing tw(RL) RESET trec(R) WAKEUP timing tw (WAKEUPL) WAKEUP Interrupt timing trec (INT) tw (INTL) INT1 - INT4 44 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 PD77110 External Data Memory Access Timing requirements Parameter Read data setup time Read data hold time Symbol tsuDDRD thDDRD Condition MIN. 18 0 TYP. MAX. Unit ns ns Switching characteristics Parameter Address cycle time Address output hold time MRD output delay time Write data output valid time Write data output hold time MWR output delay time MWR output hold time MWR low-level width MWR high-level width Symbol trcDA thDA tdDR tvDDWD thDDWD tdDW thDA twDWL twDWH 0 0 0 tcC x tcDW - 3 0.5 tcC - 3 0.5 tcC 0 5 5 Condition MIN. TYP. tcC + (tcC x tcDW) Note MAX. Unit ns ns ns ns ns ns ns ns ns Note tcDW: Number of data wait cycles Data Sheet U12801EJ4V0DS00 45 PD77110, 77111, 77112 PD77110 External data memory access timing (read) DA0 - DA14 X/Y trcDA tdDR MRD tdDR tsuDDRD D0 - D15 thDDRD External data memory access timing (write) DA0 - DA14 X/Y trcDA tdDW twDWL twDWH tdDW thDA MWR tvDDWD D0 - D15 Hi-Z tvDDWD thDDWD Hi-Z 46 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 PD77110 Bus Arbitration Timing requirements Parameter HOLDRQ setup time HOLDRQ hold time Symbol tsuHRQ thHRQ Condition MIN. 0 0 TYP. MAX. Unit ns ns Switching characteristics Parameter BSTB hold time BSTB output delay time HOLDAK output delay time Data hold time during bus arbitration Data valid time during bus arbitration Symbol thBS tdBS tdHAK th (BS-D) Condition MIN. 0 20 18 25 TYP. MAX. Unit ns ns ns ns tv (BS-D) 25 ns Data Sheet U12801EJ4V0DS00 47 PD77110, 77111, 77112 PD77110 Bus arbitration timing (when bus is idle) CLKIN (Bus busy) thBS BSTB tsuHRQ HOLDRQ tdHAK HOLDAK th (BS-D) X/Y, DA0 - DA14, MRD, MWR Hi-Z tv (BS-D) tdHAK thHRQ tsuHRQ thHRQ Bus idle tdBS Bus release Bus idle (Bus busy) Bus arbitration timing (when bus is busy) CLKIN (Bus busy) Bus busy Bus idle Bus release Bus idle (Bus busy) thBS BSTB tsuHRQ HOLDRQ tdBS tsuHRQ thHRQ thHRQ tdHAK HOLDAK th (BS-D) X/Y, DA0 - DA14, MRD, MWR Hi-Z tdHAK tv (BS-D) 48 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 PD77110 Serial Interface Timing requirements Parameter SCK cycle time SCK high-/low-level width SCK rise/fall time SOEN setup time SOEN hold time SIEN setup time SIEN hold time SI setup time SI hold time Symbol tcSC twSC trtSC tsuSOE thSOE tsuSIE thSIE tsuSI thSI 5 10 5 10 5 10 Condition MIN. 60 25 20 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns Switching characteristics Parameter SORQ output delay time SORQ hold time SO output delay time SO hold time SIAK output delay time SIAK hold time Symbol tdSOR thSOR tdSO thSO tdSIA thSIA 0 0 25 0 25 Condition MIN. TYP. MAX. 25 Unit ns ns ns ns ns ns Caution If noise is superimposed on the serial clock, the serial interface may be deadlocked. Bear in mind the following points when designing your system: * Reinforce the wiring for power supply and ground (if noise is superimposed on the power and ground lines, it has the same effect as if noise were superimposed on the serial clock). * Shorten the wiring between the device's SCK1 and SCK2 pins, and clock supply source. * Do not cross the signal lines of the serial clock with any other signal lines. Do not route the serial clock line in the vicinity of a line through which a high alternating current flows. * Supply the clock to the SCK1 and SCK2 pins of the device from the clock source on a one-toone basis. Do not supply clock to several devices from one clock source. * Exercise care that the serial clock does not overshoot or undershoot. In particular, make sure that the rising and falling of the serial clock waveform are clear. x Make sure that the serial clock rises and falls linearly. The serial clock must not bound. Noise must not be superimposed on the serial clock. x The serial clock must not rise or fall step-wise. Data Sheet U12801EJ4V0DS00 49 PD77110, 77111, 77112 PD77110 Serial output timing 1 tcSC twSC SCK1, SCK2 twSC trfSC trfSC tdSOR thSOR SORQ1 tsuSOE tsuSOE thSOE SOEN1, SOEN2 tdSO SO1, SO2 Hi-Z 1st tdSO Last thSO thSOE Serial output timing 2 (during successive output) tcSC twSC SCK1, SCK2 twSC trfSC trfSC tdSOR thSOR SORQ1 tsuSOE thSOE SOEN1, SOEN2 tdSO SO1, SO2 Last 1st Last thSO Hi-Z 50 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 PD77110 Serial input timing 1 tcSC twSC SCK1, SCK2 twSC trfSC trfSC tdSIA thSIA SIAK1 tsuSIE tsuSIE SIEN1, SIEN2 thSIE thSIE tsuSI SI1, SI2 1st thSI 2nd 3rd Serial input timing 2 (during successive input) tcSC twSC SCK1, SCK2 twSC trfSC trfSC tdSIA thSIA SIAK1 tsuSIE thSIE SIEN1, SIEN2 tsuSI SI1, SI2 thSI Last-1 Last 1st 2nd 3rd Data Sheet U12801EJ4V0DS00 51 PD77110, 77111, 77112 PD77110 Host Interface Timing requirements Parameter HRD delay time HRD width HCS, HA0, HA1, read hold time HCS, HA0, HA1 line hold time HRD, HWR recovery time HWR delay time HWR width HWR hold time HWR setup time Symbol tdHR twHR thHCAR Condition MIN. 10 60 0 TYP. MAX. Unit ns ns ns thHCAW trecHS tdHW twHW thHDW tsuHDW 0 60 10 60 0 10 ns ns ns ns ns ns Switching characteristics Parameter HRE, HWE output delay time HRE, HWE hold time HRD valid time HRD hold time Symbol tdHE thHE tvHDR thHDR 0 Condition MIN. TYP. MAX. 25 25 25 Unit ns ns ns ns 52 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 PD77110 Host read interface timing CLKIN HCS, HA0, HA1 thHCAR tdHR HRD thHDR Hi-Z tdHE tvHDR Hi-Z twHR trecHS HD0 - HD7 thHE HRE Host write interface timing CLKIN HCS, HA0, HA1 thHCAW tdHW HWR thHDW tsuHDW HD0 - HD7 tdHE twHW trecHS thHE HWE Data Sheet U12801EJ4V0DS00 53 PD77110, 77111, 77112 PD77110 General-purpose I/O Port Timing requirements Parameter Port input setup time Port input hold time Symbol tsuPI thPI Condition MIN. 0 10 TYP. MAX. Unit ns ns Switching characteristics Parameter Port output delay time Symbol tdPO Condition MIN. TYP. MAX. 25 Unit ns General-purpose I/O port timing CLKIN tdPO P0 - P3 (Output) tsuPI thPI P0 - P3 (Input) 54 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 PD77110 Debugging Interface (JTAG) Timing requirements Parameter TCK cycle time TCK high-/low-level width TCK rise/fall time TMS, TDI setup time TMS, TDI hold time Input pin setup time Input pin hold time TRST setup time Symbol tcTCK twTCK trfTCK tsuDI thDI tsuJIN thJIN tsuTRST 20 20 20 20 100 Condition MIN. 120 50 20 TYP. MAX. Unit ns ns ns ns ns ns ns ns Switching characteristics Parameter TDO output delay time Output pin output delay time Symbol tdDO tdJOUT Condition MIN. TYP. MAX. 20 20 Unit ns ns Debugging interface timing tcTCK twTCK TCK tsuTRST TRST tsuDI thDI TMS, TDI Valid tdDO TDO tsuJIN thJIN Capture state Valid tdJOUT Update state Valid Valid twTCK trfTCK trfTCK Remark For details of JTAG, refer to IEEE1149.1. Data Sheet U12801EJ4V0DS00 55 PD77110, 77111, 77112 PD77111, 77112 (2) PD77111, 77112 AC Characteristics (TA = -40 to +85C, with IVDD and EVDD within recommended operating condition range) Clock Timing requirements Parameter CLKIN cycle time Note 1 Symbol tcCX Condition MIN. 25 TYP. MAX. Unit ns PLL lock Note 2 range IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V 25 x m 10 x m 50 x m 50 x m ns ns CLKIN high-level width CLKIN low-level width CLKIN rise/fall time Internal clock cycle time Note 3 requirements twCXH twCXL trfCX tcC (R) IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V 12.5 12.5 5 25 13.3 ns ns ns ns ns Notes 1. m: Multiple, n: Division ratio 2. This is the range in which the PLL is locked (stably oscillates). Input tcCX within this range. 3. Input tcCX so that the value of (tcCX / m x n) satisfies this condition. Switching characteristics Parameter Internal clock cycle Note Symbol tcC Condition During normal operation In HALT mode MIN. TYP. tcCX x n / m tcCX x n / m x l tcC MAX. Unit ns ns ns ns ns CLKOUT cycle time CLKOUT width tcCO twCO During normal operation n = 1, or even number n = odd number (other than 1) tcCX / 2 - 3 tcCX / m - 3 tcCX / m x n - 3 In HALT mode CLKOUT rise/fall time CLKOUT delay time trfCO tdCO IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V ns 5 20 15 ns ns ns Note m: Multiple, n: Division ratio, l: HALT division ratio 56 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 PD77111, 77112 Clock I/O timing tcCX twCXH twCXL trfCX trfCX CLKIN tcC, tcC(R) Internal clock tcCO tdCO twCO twCO trfCO trfCO CLKOUT Data Sheet U12801EJ4V0DS00 57 PD77110, 77111, 77112 PD77111, 77112 Reset, Interrupt Timing requirements Parameter RESET low-level width Symbol tw (RL) Condition On power application in STOP mode During normal operation, in HALT mode RESET recovery time trec (R) On power application Note 4 Note 1 MIN. , 100 + 2048tcCX 4tcC Note 2 TYP. MAX. Unit s Note 3 ns 4tcCX 4tcC Note 2 ns ns WAKEUP low-level width INT1 - INT4 low-level width INT1 - INT4 recovery time tw (WAKEUPL) tw (INTL) trec (INT) 100 3tcC Note 2 s ns ns 3tcC Notes 1. The value on power application is the time from when the supply voltages have reached IVDD = 1.8 V and EVDD = 2.7 V. A stable clock input is also required. 2. Note that tcC is I (I = integer of 1 to 16) times that during normal operation in the HALT mode. 3. If the low-level width of RESET is greater than 1024tcC, the PLL initialization mode is triggered. If there is no need to use the PLL initialization mode, set the width to less than 1024tcC. 4. When the power is turned on, a recovery period of 4tcCX is necessary before inputting RESET. Reset timing tw(RL) RESET trec(R) WAKEUP timing tw (WAKEUPL) WAKEUP Interrupt timing trec(INT) tw(INTL) INT1 - INT4 58 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 PD77111, 77112 External Data Memory Access (PD77112 only) Timing requirements Parameter Read data setup time Read data hold time Symbol tsuDDRD thDDRD Condition MIN. 18 0 TYP. MAX. Unit ns ns Switching characteristics Parameter Address cycle time Address output hold time MRD output delay time Write data output valid time Write data output hold time MWR output delay time MWR output hold time MWR low-level width MWR high-level width Symbol trcDA thDA tdDR tvDDWD thDDWD tdDW thDA twDWL twDWH 0 0 0 tcC x tcDW - 3 0.5 tcC - 3 0.5 tcC 0 5 5 Condition MIN. TYP. tcC + (tcC x tcDW) Note MAX. Unit ns ns ns ns ns ns ns ns ns Note tcDW: Number of data wait cycles Data Sheet U12801EJ4V0DS00 59 PD77110, 77111, 77112 PD77111, 77112 External data memory access timing (read) DA0 - DA13 X/Y trcDA tdDR MRD tdDR tsuDDRD D0 - D15 thDDRD External data memory access timing (write) DA0 - DA13 X/Y trcDA tdDW twDWL twDWH tdDW thDA MWR tvDDWD D0 - D15 Hi-Z tvDDWD thDDWD Hi-Z 60 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 PD77111, 77112 Bus Arbitration (PD77112 only) Timing requirements Parameter HOLDRQ setup time HOLDRQ hold time Symbol tsuHRQ thHRQ Condition MIN. 0 0 TYP. MAX. Unit ns ns Switching characteristics Parameter BSTB hold time BSTB output delay time HOLDAK output delay time Data hold time during bus arbitration Data valid time during bus arbitration Symbol thBS tdBS tdHAK th (BS-D) Condition MIN. 0 20 18 25 TYP. MAX. Unit ns ns ns ns tv (BS-D) 25 ns Data Sheet U12801EJ4V0DS00 61 PD77110, 77111, 77112 PD77111, 77112 Bus arbitration timing (when bus is idle) CLKIN (Bus busy) thBS BSTB tsuHRQ HOLDRQ tdHAK HOLDAK th (BS-D) X/Y, DA0 - DA13, MRD, MWR Hi-Z tv (BS-D) tdHAK thHRQ tsuHRQ thHRQ Bus idle tdBS Bus release Bus idle (Bus busy) Bus arbitration timing (when bus is busy) CLKIN (Bus busy) Bus busy Bus idle Bus release Bus idle (Bus busy) thBS BSTB tsuHRQ HOLDRQ tdBS tsuHRQ thHRQ thHRQ tdHAK HOLDAK th (BS-D) X/Y, DA0 - DA13, MRD, MWR Hi-Z tdHAK tv (BS-D) 62 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 PD77111, 77112 Serial Interface Timing requirements Parameter SCK cycle time SCK high-/low-level width SCK rise/fall time SOEN setup time Symbol tcSC twSC trfSC tsuSOE IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V SOEN hold time thSOE IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V SIEN setup time tsuSIE IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V SIEN hold time thSIE IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V SI setup time tsuSI IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V SI hold time thSI IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V 10 5 15 10 10 5 15 10 10 5 15 10 Condition MIN. 60 25 20 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Switching characteristics Parameter SORQ output delay time Symbol tdSOR Condition IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V SORQ hold time SO output delay time thSOR tdSO IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V SO hold time SIAK output delay time thSO tdSIA IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V SIAK hold time thSIA 0 0 30 25 0 30 25 MIN. TYP. MAX. 30 25 Unit ns ns ns ns ns ns ns ns ns Data Sheet U12801EJ4V0DS00 63 PD77110, 77111, 77112 PD77111, 77112 Caution If noise is superimposed on the serial clock, the serial interface may be deadlocked. Bear in mind the following points when designing your system: * Reinforce the wiring for power supply and ground (if noise is superimposed on the power and ground lines, it has the same effect as if noise were superimposed on the serial clock). * Shorten the wiring between the device's SCK1 and SCK2 pins, and clock supply source. * Do not cross the signal lines of the serial clock with any other signal lines. Do not route the serial clock line in the vicinity of a line through which a high alternating current flows. * Supply the clock to the SCK1 and SCK2 pins of the device from the clock source on a one-toone basis. Do not supply clock to several devices from one clock source. * Exercise care that the serial clock does not overshoot or undershoot. In particular, make sure that the rising and falling of the serial clock waveform are clear. x Make sure that the serial clock rises and falls linearly. The serial clock must not bound. Noise must not be superimposed on the serial clock. x The serial clock must not rise or fall step-wise. 64 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 PD77111, 77112 Serial output timing 1 tcSC twSC SCK1, SCK2 twSC trfSC trfSC tdSOR thSOR SORQ1 tsuSOE tsuSOE thSOE thSOE SOEN1, SOEN2 tdSO SO1, SO2 Hi-Z 1st tdSO Last thSO Serial output timing 2 (during successive output) tcSC twSC SCK1, SCK2 twSC trfSC trfSC tdSOR thSOR SORQ1 tsuSOE thSOE SOEN1, SOEN2 tdSO SO1, SO2 Last 1st Last thSO Data Sheet U12801EJ4V0DS00 65 PD77110, 77111, 77112 PD77111, 77112 Serial input timing 1 tcSC twSC SCK1, SCK2 twSC trfSC trfSC tdSIA thSIA SIAK1 tsuSIE tsuSIE SIEN1, SIEN2 thSIE thSIE tsuSI SI1, SI2 1st thSI 2nd 3rd Serial input timing 2 (during successive input) tcSC twSC SCK1, SCK2 twSC trfSC trfSC tdSIA thSIA SIAK1 tsuSIE thSIE SIEN1, SIEN2 tsuSI SI1, SI2 thSI Last-1 Last 1st 2nd 3rd 66 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 PD77111, 77112 Host Interface Timing requirements Parameter HRD delay time Symbol tdHR Condition IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V HRD width HCS, HA0, HA1, read hold time HCS, HA0, HA1 line hold time HRD, HWR recovery time HWR delay time twHR thHCAR MIN. 15 10 60 0 TYP. MAX. Unit ns ns ns ns thHCAW trecHS tdHW IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V 0 60 15 10 60 0 IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V 15 10 ns ns ns ns ns ns ns ns HWR width HWR hold time HWR setup time twHW thHDW tsuHDW Switching characteristics Parameter HRE, HWE output delay time Symbol tdHE Condition IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V HRE, HWE hold time thHE IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V HRD valid time tvHDR IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V HRD hold time thHDR 0 MIN. TYP. MAX. 30 25 30 25 30 25 Unit ns ns ns ns ns ns ns Data Sheet U12801EJ4V0DS00 67 PD77110, 77111, 77112 PD77111, 77112 Host read interface timing CLKIN HCS, HA0, HA1 thHCAR tdHR HRD thHDR Hi-Z tdHE tvHDR Hi-Z twHR trecHS HD0 - HD7 thHE HRE Host write interface timing CLKIN HCS, HA0, HA1 thHCAW tdHW HWR thHDW tsuHDW HD0 - HD7 tdHE twHW trecHS thHE HWE 68 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 PD77111, 77112 General-purpose I/O Port Timing requirements Parameter Port input setup time Port input hold time Symbol tsuPI thPI IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V Condition MIN. 0 15 10 TYP. MAX. Unit ns ns ns Switching characteristics Parameter Port output delay time Symbol tdPO Condition IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V MIN. TYP. MAX. 30 25 Unit ns ns General-purpose I/O port timing CLKIN tdPO P0 - P3 (Output) tsuPI thPI P0 - P3 (Input) Data Sheet U12801EJ4V0DS00 69 PD77110, 77111, 77112 Debugging Interface (JTAG) Timing requirements Parameter TCK cycle time TCK high-/low-level width TCK rise/fall time TMS, TDI setup time Symbol tcTCK twTCK trfTCK tsuDI IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V TMS, TDI hold time thDI IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V Input pin setup time tsuJIN IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V Input pin hold time thJIN IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V TRST setup time tsuTRST 25 20 25 20 25 20 25 20 100 Condition MIN. 120 50 20 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns Switching characteristics Parameter TDO output delay time Symbol tdDO Condition IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V Output pin output delay time tdJOUT IVDD = 1.8 to 2.7 V IVDD = 2.3 to 2.7 V MIN. TYP. MAX. 25 20 25 20 Unit ns ns ns ns 70 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 Debugging interface timing tcTCK twTCK twTCK trfTCK trfTCK TCK tsuTRST TRST tsuDI thDI TMS, TDI Valid Valid Valid tdDO TDO tsuJIN thJIN Capture state Valid tdJOUT Update state Remark For details of JTAG, refer to IEEE1149.1. Data Sheet U12801EJ4V0DS00 71 PD77110, 77111, 77112 11. PACKAGE 100-PIN PLASTIC TQFP (FINE PITCH) (14x14) A B 75 76 51 50 detail of lead end S C D Q R 100 1 26 25 F G H P I M J K N S L M NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 16.00.2 14.00.2 14.00.2 16.00.2 1.0 1.0 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.00.2 0.50.2 0.145+0.055 -0.045 0.10 1.00.1 0.10.05 3 +7 -3 1.27 MAX. S100GC-50-9EU-2 72 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 80-PIN PLASTIC TQFP (FINE PITCH) (12x12) A B 60 61 41 40 detail of lead end S C D Q R 80 1 20 21 F G H P I M J K S N S L M NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 14.00.2 12.00.2 12.00.2 14.00.2 1.25 1.25 0.220.05 0.10 0.5 (T.P.) 1.00.2 0.50.2 0.1450.05 0.10 1.00.05 0.10.05 3 +7 -3 1.2 MAX. S80GK-50-9EU-1 Data Sheet U12801EJ4V0DS00 73 PD77110, 77111, 77112 80-PIN PLASTIC FBGA (9x9) A B W SB B A C D 9 8 7 6 5 4 3 2 1 JHGFEDCBA Q Index mark P W SA J I R Y1 S H ITEM A B C D MILLIMETERS 9.000.10 8.40 8.40 9.000.10 1.30 0.8 (T.P.) 0.350.1 0.36 0.96 1.310.15 0.10 S E F G K S F L E G H I J K L M P Q R W Y1 M M SAB 0.50+0.05 -0.10 0.08 C1.0 R0.3 25 0.20 0.20 S80F1-80-CN1-1 74 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 12. RECOMMENDED SOLDERING CONDITIONS It is recommended to solder this product under the following conditions. For details of the recommended soldering conditions, refer to information document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E). For soldering methods and conditions other than those recommended, consult NEC. Surface mount type PD77110GC-9EU: 100-pin plastic TQFP (fine pitch) (14 x 14 mm) PD77111GK-xxx-9EU: 80-pin plastic TQFP (fine pitch) (12 x 12 mm) Process Infrared ray reflow Conditions Package peak temperature: 235C, Time: 30 seconds MAX (210C MIN), Note Number of times: 2 MAX, Number of days: 3 (after that, prebaking is necessary for 10 hours) VPS Package peak temperature: 215C, Time: 30 seconds MAX (210C MIN), Note Number of times: 2 MAX, Number of days: 3 (after that, prebaking is necessary for 10 hours) Partial heating method Pin temperature: 300C MAX, Time: 3 seconds MAX (per side of device) - VP15-103-2 Symbol IR35-103-2 PD77112GC-xxx-9EU: 100-pin plastic TQFP (fine pitch) (14 x 14 mm) Process Infrared ray reflow Conditions Package peak temperature: 235C, Time: 30 seconds MAX (210C MIN), Note Number of times: 3 MAX, Number of days: 7 (after that, prebaking is necessary for 10 hours) VPS Package peak temperature: 215C, Time: 30 seconds MAX (210C MIN), Note Number of times: 3 MAX, Number of days: 7 (after that, prebaking is necessary for 10 hours) Partial heating method Pin temperature: 300C MAX, Time: 3 seconds MAX (per side of device) - VP15-107-3 Symbol IR35-107-3 Note Number of days in storage after the dry pack has been opened. The storage conditions are at 25C, 65% RH MAX. Caution Do not use two or more soldering methods in combination (except partial heating method). Data Sheet U12801EJ4V0DS00 75 PD77110, 77111, 77112 PD77111F1-xxx-CN1: 80-pin plastic fine-pitch BGA (9 x 9 mm) Process Infrared ray reflow Conditions Package peak temperature: 230C, Time: 30 seconds MAX (210C MIN), Note Number of times: 2 MAX, Number of days: 3 (after that, prebaking is necessary for 10 hours) VPS Package peak temperature: 215C, Time: 30 seconds MAX (210C MIN), Note Number of times: 2 MAX, Number of days: 3 (after that, prebaking is necessary for 10 hours) VP15-103-2 Symbol IR30-103-2 Note Number of days in storage after the dry pack has been opened. The storage conditions are at 25C, 65% RH MAX. Caution Do not use two or more soldering methods in combination (except partial heating method). 76 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 [MEMO] Data Sheet U12801EJ4V0DS00 77 PD77110, 77111, 77112 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 78 Data Sheet U12801EJ4V0DS00 PD77110, 77111, 77112 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * * * * * Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements * In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J99.1 Data Sheet U12801EJ4V0DS00 79 PD77110, 77111, 77112 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. License not needed : PD77110GC-9EU The customer must judge the need for license: PD77111GK-xxx-9EU, PD77111F1-xxx-CN1, PD77112GC-xxx-9EU * The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98. 8 |
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